Phase-Locked Loops

Why lock an oscillator?

A reference oscillator can be accurate and quiet but at the wrong frequency. A voltage-controlled oscillator (VCO) can reach the frequency a radio or clock tree needs, but it drifts with tuning voltage, temperature, supply noise, and time. A phase-locked loop (PLL) combines them: it continually compares their timing and corrects the tunable oscillator.

The useful mental model is not a bag of named circuit blocks. It is a negative-feedback system that turns phase error into frequency correction.

That idea gives this article its order:

1. watch frequency error accumulate as phase error,
2. follow one correction around the loop,
3. use dividers to define the locked frequency,
4. shape the near-lock transient,
5. choose which noise source the output follows,
6. debug the nonlinear hardware that the tidy model leaves out.

Frequency is the slope of phase

Phase remembers every cycle an oscillator has accumulated:

$$\phi(t)=\phi(0)+2\pi\int_0^t f(\tau)\,d\tau$$

Define the comparison error as reference phase minus feedback phase:

$$\phi_e(t)=\phi_{\mathrm{ref}}(t)-\phi_{\mathrm{fb}}(t)$$

Its slope exposes frequency error directly:

$$\frac{d\phi_e}{dt}=2\pi\left(f_{\mathrm{ref}}-f_{\mathrm{fb}}\right)$$

If the two frequencies match, the unwrapped phase error is constant. If the feedback is slow, the error ramps upward; if it is fast, the error ramps downward. A phase-frequency detector (PFD) turns that direction into UP or DOWN activity.

Phase error is accumulated frequency error

Offset the feedback oscillator, then watch a small frequency mismatch become a steadily sloped phase error.

feedback fast · -57.6° accumulated

Feedback frequency offset

+2.0%

Initial feedback phase

+45°

Frequency verdict

feedback fast

The sign of the lower trace's slope tells which oscillator is leading.

Phase-error slope

-7.2° / cycle

Matched frequency makes this slope zero, even when a static phase offset remains.

Final detector view

-102.6°

A real phase detector wraps the accumulated error back into its measurable range.

The ±8% range is intentionally exaggerated so the drift is visible in eight cycles. Real reference and oscillator offsets are usually much smaller; the lower trace is left unwrapped to expose the accumulated phase-error slope.

The frequency offsets in the explorer are intentionally exaggerated so the slip is visible in eight cycles. Three observations carry into real designs:

• A fixed phase offset is not a frequency error. Equal edge rates can coexist with a constant phase difference.
• A phase ramp is a frequency error. Even a small rate mismatch eventually accumulates a whole cycle.
• Wrapping can hide acquisition trouble. A phase-only detector has a periodic characteristic, while the unwrapped trace reveals each cycle slip.

This is why a PFD is so useful for acquisition. Unlike a sinusoidal or XOR phase-only detector, a conventional PFD remembers edge ordering. During cycle slipping, individual UP and DOWN decisions can vary, but their average bias indicates which input is running faster.

Follow one correction around the loop

Consider one moment when the divided feedback edge arrives late:

1. The PFD asserts UP because the reference edge arrived first.
2. The charge pump sources a current pulse whose area represents the timing error.
3. The loop filter converts and accumulates that current into a smoother control voltage.
4. A positive-gain VCO speeds up as its control voltage rises.
5. Faster VCO phase accumulation advances the next divided feedback edge.
6. Negative feedback shortens later UP pulses until the average correction only supplies what the real circuit needs to remain locked.

If detector polarity or VCO gain has the opposite sign from the assumed loop, the same path becomes positive feedback and runs toward a tuning rail.

The block units are worth keeping straight:

Phase lock becomes frequency synthesis

Put a reference divider R before the PFD, a feedback divider N around the VCO, and an output divider M after the VCO. In integer-N lock:

$$f_{\mathrm{PFD}}=\frac{f_{\mathrm{ref}}}{R}$$ $$f_{\mathrm{VCO}}=Nf_{\mathrm{PFD}}$$ $$f_{\mathrm{out}}=\frac{f_{\mathrm{VCO}}}{M} =\frac{N}{RM}f_{\mathrm{ref}}$$

The loop still compares phase at one frequency. The dividers make that comparison enforce a higher VCO frequency.

Integer-N frequency plan

Choose the four integer levers, then follow the same frequency around the reference, feedback, and output paths.

fout 2.40 GHz

Reference frequency

100 MHz

Reference divider R

÷2

Feedback divider N

×96

Output divider M

÷2

PFD frequency

50.00 MHz

Reference frequency after ÷R; this sets the comparison cadence.

VCO frequency

4.80 GHz

The loop forces the VCO to N times the PFD frequency.

Output frequency

2.40 GHz

The observable output after the optional ÷M stage.

Integer step

25.00 MHz

One count of N, as seen after the output divider.

Phase multiplication

+39.6 dB

The 20 log₁₀(N) reference-path phase-noise multiplication.

Start from the explorer's 2.4 GHz plan: a 100 MHz reference divided by R = 2 produces a 50 MHz PFD rate. N = 96 locks the VCO at 4.8 GHz, and M = 2 produces 2.4 GHz. Incrementing integer N by one moves the output by 25 MHz.

The controls reveal the first frequency-planning tradeoffs:

• A higher PFD rate gives more correction opportunities and permits a lower N for the same VCO frequency, but device limits, reference spurs, and the required channel grid constrain it.
• In an integer-N loop, one count of N changes the output by $f_{\mathrm{PFD}}/M$.
• Phase perturbations at the comparison input are multiplied by approximately N at the VCO output inside the loop bandwidth, a $20\log_{10}(N)$ power-spectral-density penalty in decibels. That number is a transfer factor, not a complete phase-noise prediction.
• A fractional-N loop varies integer divider states so their average ratio can lie between integers. It creates finer resolution without forcing a tiny PFD rate, but shaped quantization noise and the potential for fractional spurs join the design problem.

An output divider changes the delivered frequency without changing the VCO's feedback ratio in this topology. Real synthesizers may place or select dividers differently, so a data-sheet block diagram always outranks a generic one.

Linearize only after the loop makes sense

Close to lock, small phase perturbations can be treated with linear control theory. A simplified charge-pump loop has an open-loop gain shaped by detector/charge-pump gain $K_\phi$, filter transimpedance $Z(s)$, VCO gain $K_{\mathrm{VCO}}$, the oscillator's frequency-to-phase integration, and feedback division:

$$L(s)=\frac{K_\phi Z(s)K_{\mathrm{VCO}}}{sN}$$

In this charge-pump form, $K_\phi$ is in A/rad, $Z(s)$ is in V/A, and $K_{\mathrm{VCO}}$ is in rad/s/V. A data-sheet gain quoted in Hz/V or MHz/V must be multiplied by $2\pi$ before it is used in this equation.

The factor $1/s$ is the key: control voltage changes frequency, and phase is the integral of frequency. The loop filter adds poles and zeros that set crossover, phase margin, peaking, and the response to disturbances.

For intuition, many near-lock responses can be compared with the canonical second-order form:

$$H_2(s)=\frac{\omega_n^2}{s^2+2\zeta\omega_ns+\omega_n^2}$$

Here $\omega_n=2\pi f_n$ sets the time scale and $\zeta$ is the damping ratio. Natural frequency is not another name for loop bandwidth; their relationship depends on the actual loop transfer function and filter zeros.

Closing the loop

Hold the phase step at 90° and trade natural frequency against damping while the lock detector watches a real degree window.

50.0 µs · quick, underdamped

Natural frequency

18 kHz

Damping ratio ζ

0.65

Lock window

±3°

Percent overshoot

6.8%

6.1° beyond the commanded phase step.

Settling / lock time

50.0 µs

First sample after which all remaining error stays inside ±3°.

Response character

quick, underdamped

Lower ζ rings; higher ζ gives up speed for a more restrained approach.

This is a normalized, linearized second-order model—not an acquisition or circuit simulator. It omits detector nonlinearity, cycle slips, tuning limits, saturation, noise, and sampled-loop effects.

Try the response in this order:

1. Hold $f_n$ fixed and move $\zeta$ from 0.3 through about 0.7, 1.0, and 1.3. Ringing disappears, then the response becomes increasingly slow and monotonic.
2. Hold $\zeta$ fixed and double $f_n$. The shape stays similar while the time axis compresses.
3. Tighten the lock window. The waveform does not change, but the time at which a lock detector may safely declare success moves later.

The explorer uses a 90° phase step in a normalized linear model. It correctly distinguishes underdamped, critically damped, and overdamped responses, but it is not a component-value calculator and it does not reproduce the numerator of every type-II charge-pump PLL.

Where the linear response stops helping

Far from lock, the real loop is nonlinear. A large frequency hop can involve:

• PFD and charge-pump saturation,
• phase wrapping and repeated cycle slips,
• VCO band calibration or coarse tuning,
• control-voltage rails and VCO gain variation,
• current limits and loop-filter slew,
• digital quantization and update latency,
• a lock detector asserting briefly before the loop truly settles.

Terms such as capture range, pull-in range, lock-in range, and hold range are not universal numbers independent of topology and test method. A safer acquisition story is chronological:

1. Confirm the target lies inside a calibrated VCO tuning band.
2. Let the PFD establish the direction of the frequency error.
3. Drive the control node until the PFD input rates nearly match.
4. Enter the near-lock region where the linear model becomes useful.
5. Qualify phase or frequency error for enough comparison cycles before asserting lock.

This distinction prevents a common category error: a beautifully damped small-signal plot cannot prove that a synthesizer will acquire from a cold start.

Loop bandwidth is a noise boundary

Feedback also decides which oscillator the output resembles at each offset from the carrier.

Because $L(s)$ already includes the divider feedback factor $1/N$, phase at the PFD's reference input transfers to VCO phase as:

$$H_{\mathrm{ref\to VCO}}(s)=N\frac{L(s)}{1+L(s)}$$

Divide out that N gain to compare the two complementary shapes:

$$H_{\mathrm{loop,norm}}(s)=\frac{L(s)}{1+L(s)}$$ $$H_{\mathrm{VCO}}(s)=\frac{1}{1+L(s)}$$

Inside the loop bandwidth, the loop strongly corrects the VCO, so reference, PFD, charge-pump, and divider noise can dominate after their gain factors. Far outside the bandwidth, the loop cannot correct rapid VCO phase motion, so the output approaches the free-running VCO noise. When the delivered output is taken after an ideal divider M, its phase deviation is also divided by M.

Loop bandwidth is a noise crossover

Move the crossover between reference-path noise inside the loop and free-running VCO noise outside it.

100.0 kHz · above: reference path

Loop bandwidth

100.0 kHz

Reference-path floor

-110.0 dBc/Hz

Loop bandwidth

100.0 kHz

The illustrative low-pass and high-pass contributions are each about −3 dB here.

At the crossover

reference path

-110.9 dBc/Hz combined near 100.0 kHz.

One decade above

reference path

-127.9 dBc/Hz at 1.0 MHz.

This is a shape-and-tradeoff model, not a device prediction. Its illustrative free-running VCO is −72 dBc/Hz at 1 kHz, falls 20 dB per decade, and stops at a −162 dBc/Hz floor; real devices add corners, spurs, divider noise, and implementation-specific transfer functions.

This explorer uses complementary first-order transfer shapes and illustrative source spectra. It teaches the crossover, not a particular IC or a universal optimum.

A real noise design needs measured or modeled spectra for the reference, PFD/charge pump, divider, VCO, supplies, and buffers. Independent or uncorrelated noise contributions must be converted to linear power before they are summed; adding dBc/Hz values directly is wrong. Correlated terms need their cross-spectral relationship, and deterministic spurs belong in a separate analysis.

Close the loop on settling and noise

The response and noise explorers are two views of the same loop-shaping decision. The first varies the natural frequency $f_n$ and damping ratio $\zeta$ of a canonical second-order response. The second varies an illustrative loop bandwidth $f_{\mathrm{BW}}$ to move the noise crossover. Those frequencies are related by the actual open-loop transfer function, but they are not interchangeable: loop order, filter zeros, damping, and gain determine the mapping between them.

For an underdamped loop that is already near lock, the settling envelope has the useful scaling

$$t_s \propto \frac{1}{\omega_n}$$

for a fixed damping ratio, initial step, and normalized error window. Doubling $\omega_n$ therefore roughly halves that part of the settling time. Too little damping creates ringing; moving well past critical damping introduces a slow pole and does not make the loop indefinitely faster. Most importantly, this estimate covers only the final linear portion of a frequency change. Programming latency, VCO calibration, nonlinear acquisition, cycle slips, control-node slew, and lock-detector qualification can dominate total tuning time.

The noise score is an area, not the height of one point on the plot. After each source is referred to the output, shaped by its transfer function, converted to linear units, and combined appropriately, integrate over the offset-frequency band that matters to the system:

$$\sigma_\phi^2=\int_{f_1}^{f_2}S_{\phi,\mathrm{out}}(f)\,df, \qquad \sigma_t=\frac{\sigma_\phi}{2\pi f_\mathrm{out}}$$

Here $S_{\phi,\mathrm{out}}$ is the one-sided phase-fluctuation power spectral density in rad²/Hz and $\sigma_t$ is RMS time jitter. When starting from single-sideband phase noise in dBc/Hz, convert it to linear units using a stated convention before integrating.

This is more precise than “wide is fast but noisy.” In the explorer's fixed, adequately damped complementary-transfer model, widening the loop improves output noise where the adjusted reference path is quieter than the VCO and worsens it where that ordering reverses. Real higher-order loops can add peaking and source-specific transfer functions, so the source-noise crossing is a useful starting point, not a universal optimum.

A practical iteration keeps both scorecards open:

1. Use the response view to choose damping, define the final error window and hold time, and estimate the required near-lock speed.
2. Translate that target into candidate real loop filters, then calculate and integrate the output-referred noise for each candidate over the required offset band.
3. Reject candidates that fail phase margin, nonlinear acquisition, spur, or operating-corner checks; choose from the region that passes both the time and noise budgets.

If no candidate passes both budgets, the answer is not hidden between two slider positions. Improve a dominant noise source, change the frequency plan or charge-pump/filter design, select a different VCO, or revisit the system requirements.

Spurs are not phase noise

Phase noise is broadband random energy around the carrier. Spurs are discrete tones. A spectrum can pass one requirement and fail the other.

Common mechanisms include:

• Reference/PFD spurs: periodic charge-pump activity, leakage, feedthrough, or coupling near multiples of the comparison rate.
• Fractional spurs: periodic patterns or nonlinear mixing associated with fractional divider modulation.
• Integer-boundary spurs: interactions that become troublesome near an integer channel boundary in some fractional-N devices.
• External spurs: supply ripple, digital clocks, crosstalk, or reference/output coupling into the VCO tuning path.

Loop bandwidth affects how strongly some of these disturbances reach the VCO, but it does not turn a spur problem into a random-noise problem. Frequency planning, charge-pump settings, filter impedance, layout, shielding, and supply design all matter.

A lab-debugging ladder

When a PLL refuses to lock, inspect the loop in causal order instead of repeatedly rewriting configuration registers:

1. Verify the reference. Measure frequency, amplitude, edge quality, and the programmed reference path.
2. Recompute R, N, and M. Confirm the PFD, VCO, and output frequencies—not only the requested output.
3. Compare the PFD inputs. Their edge rates immediately reveal a divider or VCO-range mistake.
4. Check detector polarity and charge-pump activity. A loop driving away from the target often has the wrong sign or a disconnected path.
5. Measure the tuning voltage. A control node at a rail points toward range, calibration, polarity, or loading trouble.
6. Confirm VCO band and gain margin. Test across frequency, temperature, supply, and process corners rather than at one nominal point.
7. Measure settling honestly. Define the frequency or phase window and how long the signal must remain inside it.
8. Then inspect the spectrum. Check phase noise, reference spurs, fractional spurs, and external coupling under the real supply and layout conditions.

Design workflow

A practical PLL design pass follows the same sequence as the article:

1. Specify output frequencies, step size, settling window, integrated phase noise or jitter, and spur limits.
2. Choose a reference and R/N/M plan that keeps the PFD and VCO inside their legal ranges.
3. Select or characterize the VCO using tuning range, $K_{\mathrm{VCO}}$, phase noise, pushing, pulling, and control-voltage margin.
4. Design the loop filter from the actual detector, charge-pump, divider, and VCO models; verify phase margin and component tolerances.
5. Simulate both nonlinear acquisition and linearized noise transfer with vendor or system models.
6. Lay out the reference, charge pump, loop filter, VCO, supplies, and digital aggressors as one sensitive system.
7. Measure frequency plan, acquisition, settling, phase noise, and spurs over operating corners.

The unifying question is always the same: what phase error is being measured, what correction does it create, and what prevents that correction from producing the desired output?

References

• P. V. Brennan, Phase-Locked Loops: Principles and Practice, McGraw-Hill, 1996. ISBN record
• Analog Devices, MT-086: Fundamentals of Phase Locked Loops
• Analog Devices, Phase-Locked Loop Fundamentals
• Analog Devices, Phase-Locked Loops for High-Frequency Receivers and Transmitters—Part 2
• Analog Devices, How to Design and Debug a Phase-Locked Loop Circuit
• Dean Banerjee, Texas Instruments, PLL Performance, Simulation, and Design

External References

• ISBN record
• MT-086: Fundamentals of Phase Locked Loops
• Phase-Locked Loop Fundamentals
• Phase-Locked Loops for High-Frequency Receivers and Transmitters—Part 2
• How to Design and Debug a Phase-Locked Loop Circuit
• PLL Performance, Simulation, and Design